An SOI wafer usable for RF (Radio Frequency) high frequency) devices has been achieved by increasing the resistivity of a base wafer. However, to meet further acceleration, it is required to deal with higher frequency, and the use of the conventional high-resistivity wafer alone is becoming unsatisfactory.
It is therefore suggested as measures to add a layer that has an effect of eliminating generated carriers (a carrier trapping layer) just under a buried oxide film layer (a BOX layer) of an SOI wafer, and it is becoming necessary to form a polycrystalline silicon layer having high resistivity on a base wafer to recombine carriers generated in the high-resistivity wafer.
Patent Document 1 describes forming a polycrystalline silicon layer or an amorphous silicon layer as the carrier trapping layer at an interface between a BOX layer and a base wafer.
On the other hand, Patent Document 2 also describes forming a polycrystalline silicon layer as the carrier trapping layer at an interface between a BOX layer and a base wafer; furthermore, heat treatment temperature after forming the polycrystalline silicon layer is restricted to prevent recrystallization of the polycrystalline silicon layer.
Moreover, Patent Document 3 does not describe forming a polycrystalline silicon layer or an amorphous silicon layer as the carrier trapping layer, but describes increasing the surface roughness of a base wafer surface on the side to be bonded to a bond wafer, thereby providing the same effect as the carrier trapping layer.
With regard to a method for producing a base wafer for manufacturing an SOT wafer usable for RF devices, Patent Document 4 describes forming a dielectric layer on a silicon substrate having a high resistivity more than 500 Ωcm, and forming a polycrystalline silicon layer on the dielectric layer while depositing it at 900° C. or less.
Patent Document 5 describes forming a dielectric material layer of thickness of 0.5 to 10 nm different, from a native oxide film on a silicon wafer having a high resistivity more than 500 Ωcm and then forming a polycrystalline silicon layer to manufacture an SOI wafer usable for RE1 devices.